Quantization, gate dielectric and channel length effect in double-gate tunnel field-effect transistor

被引:7
作者
Mondol, Kalyan [1 ,2 ]
Hasan, Mehedi [3 ,4 ]
Siddique, Abdul Hasib [2 ,5 ]
Islam, Sharnali [6 ]
机构
[1] East West Univ, Dept Elect & Elect Engn, Dhaka 1212, Bangladesh
[2] Int Univ Scholars, Dept Elect & Elect Engn, Dhaka 1213, Bangladesh
[3] North South Univ, Dept Elect & Comp Engn, Dhaka 1229, Bangladesh
[4] Univ Sci & Technol Chittagong, Dept Elect & Elect Engn, Chattogram 4202, Bangladesh
[5] Amer Int Univ Bangladesh, Dept Elect & Elect Engn, Dhaka 1229, Bangladesh
[6] Univ Dhaka, Dept Elect & Elect Engn, Dhaka 1000, Bangladesh
关键词
Tunnel field-Effect transistor; Double gate; Quantization; Channel length; Gate dielectric; QUANTUM CONFINEMENT; FET;
D O I
10.1016/j.rinp.2022.105312
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In this work, we investigate the effects of changing device parameters such as channel length and gate dielectric of n-type double gate (DG) silicon tunneling field effect transistor (TFET). As the quantization effects can alter the device performance, our objective is to minimize the effect of it on gate capacitance. Device sub-threshold slope (SS), threshold voltage and ION/IOFF the ratio are also considered to find the performance of the device. We find that DG TFET with the short channel length, high gate dielectric material, and material with effective mass equal to or more than 0.04 mo (mo is free electron mass) shows promising performance. SS of TFET is much less than 60 mV/dec, which is the limiting factor of a conventional MOSFET. The materials having an effective mass of electrons less than 0.04 mo shows step-like behaviors, which reduce the gate capacitance. As a result, the control over the gate decreases and increases the short channel effect. Our optimized device shows that for high dielectric constant gate materials, SS is 33 mV/dec, the threshold voltage is 0.71 V and ION/IOFF ratio is 10(9).
引用
收藏
页数:4
相关论文
共 25 条
[1]  
Avci UE, 2013, 2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
[2]   Design and simulation of nanoscale double-gate TFET/tunnel CNTFET [J].
Bala, Shashi ;
Khosla, Mamta .
JOURNAL OF SEMICONDUCTORS, 2018, 39 (04)
[3]  
Bhagyashree K., 2018, INT J ADV RES ELECT, V7
[4]   Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric [J].
Boucart, Kathy ;
Ionescu, Adrian Mihai .
SOLID-STATE ELECTRONICS, 2007, 51 (11-12) :1500-1507
[5]   Double-gate tunnel FET with high-κ gate dielectric [J].
Boucart, Kathy ;
Mihai Ionescu, Adrian .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) :1725-1733
[6]   Rigorous Study of Double Gate Tunneling Field Effect Transistor Structure Based on Silicon [J].
Guenifi, N. ;
Rahi, S. B. ;
Ghodbane, T. .
MATERIALS FOCUS, 2018, 7 (06) :866-872
[7]   Extended-Source Double-Gate Tunnel FET With Improved DC and Analog/RF Performance [J].
Joshi, Tripuresh ;
Singh, Yashvir ;
Singh, Balraj .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (04) :1873-1879
[8]   Analytical modeling of subband quantization and quantum transport in very Low-dimensional dual metal double gate TFET [J].
Kanrar, Sharmistha Shee ;
Sarkar, Subir Kumar .
SUPERLATTICES AND MICROSTRUCTURES, 2021, 160 (160)
[9]   A simulation study of the influence of a high-k insulator and source stack on the performance of a double-gate tunnel FET [J].
Karbalaei, Mohammad ;
Dideban, Daryoosh ;
Heidari, Hadi .
JOURNAL OF COMPUTATIONAL ELECTRONICS, 2020, 19 (03) :1077-1084
[10]   Design and performance analysis of Dual-Gate All around Core-Shell Nanotube TFET [J].
Kumar, Naveen ;
Mushtaq, Umar ;
Amin, S. Intekhab ;
Anand, Sunny .
SUPERLATTICES AND MICROSTRUCTURES, 2019, 125 :356-364