Design of CMOS integrated circuits for radiation hardening and its application to space electronics

被引：0

作者：

Deval, Yann ^{[1
]}

Lapuyade, Herve ^{[1
]}

Rivet, Francois ^{[1
]}

机构：

[1] Univ Bordeaux, CNRS, Bordeaux INP, Lab IMS,UMR5218, Talence, France

来源：

2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2019年

关键词：

Total Ionizing Dose; radiation hardened electronics; CMOS; Single Event Upset; voltage reference; OPA; memory; THRESHOLD VOLTAGE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper addresses some design tricks that allow canceling - or at least reducing - the sensitivity of silicon integrated circuits to radiation effects. Both analog and digital circuits are here addressed. Redundancy, specific topology, system-level compensation: any combination is helpful as long as it avoids the implementation of radiation hardened specific technologies, as these are both expensive and unsuited to most of the state-of-the-art building blocks.

引用

页数：4

共 25 条

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