SEU mitigation for half-latches in Xilinx Virtex FPGAs

The performance, in-system reprogrammability, flexibility, and reduced costs of SRAM-based field programmable gate arrays (FPGAs) make them very interesting for high-speed on-orbit data processing, but, the current generation of radiation-tolerant SRAM-based FPGAs are based, on commercial-off-the-shelf technologies and, consequently, ate susceptible to single-event upset effects. In this paper, we discuss in detail the consequences of radiation-induced single-event upsets (SEUs) in the state of half-latch structures found in Xilinx Virtex FPGAs and describe methods for mitigating the effects of half-latch SEUs. One mitigation method's effectiveness is then illustrated through experimental data gathered through proton accelerator testing at Crocker Nuclear Laboratory, University of California-Davis. For the specific design and mitigation methodology tested, the mitigated design demonstrated more than an order of magnitude improvement in reliability over the, unmitigated version of the design in regards to average proton fluence until circuit failure.