An Area and Power Efficient design of Single Edge Triggered D-Flip Flop

被引：5

作者：

Sharma, Manoj ^{[1
]}

Noor, Arti ^{[1
]}

Tiwari, Shatish Chandra

Singh, Kunwar

机构：

[1] C DAC Noida, SoE, Noida, India

来源：

2009 INTERNATIONAL CONFERENCE ON ADVANCES IN RECENT TECHNOLOGIES IN COMMUNICATION AND COMPUTING (ARTCOM 2009) | 2009年

关键词：

SETFF; D Flip Flop;

D O I：

10.1109/ARTCom.2009.207

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed. Advantageously, the flip-flop is realized using only ten transistors. The flip-flop is implemented using Master-Slave configuration and can be used for lower cost memory and microprocessor chips. The 0.6-micron technology is used to implement the design and the area and power results were compared with existing SET D FFs. Simulation results indicated that the circuit is capable of significant power savings.

引用

页码：478 / +

页数：2

共 8 条

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