A complete single-chip GPS receiver with 1.6-V.24-mW radio in 0.18-um CMOS

We have developed a complete single-chip GPS receiver using 0.18-um CMOS to meet several important requirements, such as small size, low power, low cost and high sensitivity for mobile GPS applications. This is the first case in which a radio has been successfully combined with a baseband processor, such as SoC., in a GPS receiver. The GPS chip, with a total size of 6.4x6.4mm, contains a 2.3x2.0mm radio part, including RF front end, PLLs, IF functions, and 500K gates of baseband logic, including mask ROM, SRAM and Dual Port SRAM[l]. Its fabricated using 0.18-um CMOS Technology with a MM option and operates from a 1.6 to 2.0-V power supply Experimental results show a very low power consumption of, typically, 57-mW for a fully functional chip including baseband, and a high sensitivity of -150dBm. Through countermeasures for substrate coupling noise from the digital part, the high sensitivity was successfully achieved without any external INA.