A low-power class-AB Gm-C biquad stage in CMOS 40nm technology

A low-power class-AB Gm-C biquad stage has been designed using a voltage buffer based on error amplifiers and a push-pull current mirror. The class-AB architecture allows good power efficiency by lowering the required bias current. The biquad stage consumes 250 mu A from a 1.2V supply, and achieves a resonance frequency of 2.2MHz with a Q of 2. The SFDR (spurious-free dynamic range) with a two-tone test is 48dB and the SNR (signal-to-noise ratio) is 44.4dB, with a 400mVpp differential input signal. A pseudo-differential architecture allows large bandwidth and lower power consumption in the transconductance stages. The stage can be used to synthetize lowpass and bandpass filters composed of low-Q stages.