CMOS Full-Adders for Energy-Efficient Arithmetic Applications

被引：141

作者：

Aguirre-Hernandez, Mariano ^{[1
]}

Linares-Aranda, Monico ^{[2
]}

机构：

[1] Intel Corp, Commun Res Ctr Mexico, Guadalajara 45600, Jalisco, Mexico

[2] Natl Inst Astrophys Opt & Elect, Puebla 72840, Mexico

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2011年 / 19卷 / 04期

关键词：

Arithmetic; full-adder; high-speed; low-power; LOGIC; DESIGN;

D O I：

10.1109/TVLSI.2009.2038166

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18-mu m CMOS technology, and were tested using a comprehensive testbench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.

引用

页码：718 / 721

页数：4

共 17 条

[1] Energy-efficient, high performance circuits for arithmetic units [J].

Agarwal, Sundeepkumar ;

Pavankumar, V. K. ;

Yokesh, R. .

21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, :371-376

[2]

Aguirre M, 2005, SBCCI 2005: 18TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS, P166

[3] A review of 0.18-μm full adder performances for tree structured arithmetic circuits [J].

Chang, CH ;

Gu, JM ;

Zhang, MY .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (06) :686-695

[4] A COMPARISON OF CMOS CIRCUIT TECHNIQUES - DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC VERSUS CONVENTIONAL LOGIC [J].

CHU, KM ;

PULFREY, DL .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (04) :528-532

[5] Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style [J].

Goel, Sumeer ;

Kumar, Ashok ;

Bayoumi, Magdy A. .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2006, 14 (12) :1309-1321

[6]

PATEL D, 2008, P 1 INT C EM TRENDS, P463

[7] Low-voltage low-power CMOS full adder [J].

Radhakrishnan, D .

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2001, 148 (01) :19-24

[8]

Shams A, 1999, ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, P27, DOI 10.1109/ISCAS.1999.777797

[9] Performance analysis of low-power 1-bit CMOS full adder cells [J].

Shams, AM ;

Darwish, TK ;

Bayoumi, MA .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (01) :20-29

[10] A 1.5-NS 32-B CMOS ALU IN DOUBLE PASS-TRANSISTOR LOGIC [J].

SUZUKI, M ;

OHKUBO, N ;

SHINBO, T ;

YAMANAKA, T ;

SHIMIZU, A ;

SASAKI, K ;

NAKAGOME, Y .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (11) :1145-1151

← 1 2 →