CMOS Full-Adders for Energy-Efficient Arithmetic Applications

被引：137

作者：

Aguirre-Hernandez, Mariano ^{[1
]}

Linares-Aranda, Monico ^{[2
]}

机构：

[1] Intel Corp, Commun Res Ctr Mexico, Guadalajara 45600, Jalisco, Mexico

[2] Natl Inst Astrophys Opt & Elect, Puebla 72840, Mexico

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2011年 / 19卷 / 04期

关键词：

Arithmetic; full-adder; high-speed; low-power; LOGIC; DESIGN;

D O I：

10.1109/TVLSI.2009.2038166

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18-mu m CMOS technology, and were tested using a comprehensive testbench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.

引用

页码：718 / 721

页数：4

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