An FPGA based parametrisable system for parallel 2-D FFT implementation

被引：0

作者：

Uzun, IS ^{[1
]}

Amira, A ^{[1
]}

Bensaali, F ^{[1
]}

机构：

[1] Queens Univ Belfast, Sch Comp Sci, Belfast BT7 1NN, Antrim, North Ireland

来源：

CCCT 2003, VOL 3, PROCEEDINGS | 2003年

关键词：

FPGA; Handel-C; parallel 2-D FFT; real-time image processing; frequency-domain filtering;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The 2-D Fast Fourier Transform (FFT) plays an important role in many digital image processing applications. In this paper we present an investigation into the design and implementation of parallel 2-D FFT algorithm using Handel-C -a recently developed C-like programming language for compilation of high-level programs directly into FPGA hardware- in order to accelerate 2-D FFT computation targeting real-time image processing applications based on 2-D frequency domain filtering. The proposed system has been implemented and verified on the Celocixa RC1000 PCl-based FPGA development board equipped with Xilinx Virtex-2000E FPGA.

引用

页码：267 / 270

页数：4