Direct patterning of single electron tunneling transistors by high resolution electron beam lithography on highly doped molecular beam epitaxy grown silicon films

We present a fabrication method for a single electron tunneling transistor (SETT) in silicon. The process is based on bonded and etched back silicon on insulator material with a 40 nm thick highly n-doped Si layer grown by molecular beam epitaxy. The nanometer structure of the SETT is defined by electron beam lithography in combination with a two-layer resist system. The pattern is transferred by anisotropic reactive ion etching. The devices are passivated by low temperature remote plasma enhanced chemical vapor deposition of high quality silicondioxide. An extended region of low conductivity is observed even at T = 130 K in the current-voltage characteristics, outside of which a strong Coulomb staircase is visible. The Coulomb blockade is significantly affected by the applied gate voltage. Coulomb oscillations of the blockade width with gate potential are observed. (C) 1998 American Vacuum Society. [S0734-211X(98)04606-X].