ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-μm CMOS technology

被引:17
作者
Salman, AA
Gauthier, R
Putnam, C
Riess, P
Muhammad, M
Ioannou, DE
机构
[1] George Mason Univ, Dept Elect & Comp Engn, Fairfax, VA 22030 USA
[2] IBM Microelect, Semicond Res & Dev Ctr, Essex Jct, VT 05452 USA
[3] Infineon Technol, Hopewell Jct, NY 12533 USA
[4] OAO Serv Inc, Durham, NC 27713 USA
基金
美国国家科学基金会;
关键词
electrostatic-discharge (ESD) failure mechanisms; ESD self-protection; latent oxide damage; oxide breakdown; reliability;
D O I
10.1109/TDMR.2003.815275
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Historically, the failure mode of the nMOS/lateral n-p-n (L-npn) bipolar junction transistor (BJT) due to electrostatic discharge (ESD) is source-to-drain filamentation, as the temperature exceeds the melting temperature of silicon. However, as the gate-oxide thickness shrinks, the ESD failure changes over to oxide breakdown. In this paper, transmission line pulse (TLP) testing is combined with measurements of various leakage currents and numerical simulations of the electric field to examine the failure mode of an advanced 0.1-mum CMOS technology, which is shown to be through gate-oxide breakdown. It is also shown by I-D-V-G and I-G-V-G measurements that the application of nondestructive ESD pulses causes gradual degradation of the oxide well before failure is reached, under the (leakage current) failure criteria used. Finally, the latent effects of stress-induced oxide degradation on the failure current I-f of the nMOS/L-npn are studied, and it is shown that is the device ages from an oxide perspective, its ESD protection capabilities decrease.
引用
收藏
页码:79 / 84
页数:6
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