Design of Low Power UWB LNA for Frequency 3.1-5 GHz in 0.18 μm CMOS Technology

被引：0

作者：

Sahu, Akanksha ^{[1
]}

Sau, Paresh Chandra ^{[2
]}

Kalra, Dheeraj ^{[2
]}

机构：

[1] GLA Univ, Deparment ECE, Mathura, India

[2] GLA Univ, Dept ECE, Mathura, India

来源：

2015 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION & AUTOMATION (ICCCA) | 2015年

关键词：

CMOS; LNA; UWB; NF;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper present 3.1-5 GHz low noise amplifier (LNA) for UWB receivers. In this proposed circuit, cascade and cascode topology with modified input matching are designed. Proposed LNA achieves a maximum gain 22.252 dB, a noise figure 0.921-1.646 dB with a wide input matching. The power consumption is low under a 1.6-V dc power supply. The proposed UWB LNA is implemented using 0.18 mu m based CMOS technology under TSMC.

引用

页码：198 / 201

页数：4

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