Optimization of Stacked Nanoplate FET for 3-nm Node

被引：11

作者：

Kim, Hyunsuk ^{[1
,2
]}

Son, Dokyun ^{[1
,2
]}

Myeong, Ilho ^{[1
,2
]}

Park, Jaeyeol ^{[1
,2
]}

Kang, Myounggon ^{[3
]}

Jeon, Jongwook ^{[4
]}

Shin, Hyungcheol ^{[1
,2
]}

机构：

[1] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul 151742, South Korea

[2] Seoul Natl Univ, Sch Elect Engn & Comp Sci, Seoul 151742, South Korea

[3] Korea Natl Univ Transportat, Dept Elect Engn, Chungju Si 151742, South Korea

[4] Konkuk Univ, Dept Elect Engn, Seoul 05029, South Korea

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2020年 / 67卷 / 04期

关键词：

MOS devices; Field effect transistors; Degradation; Delays; Performance evaluation; Capacitance; Calibration; FinFET; nanoplate FET; self-heating effects (SHEs);

D O I：

10.1109/TED.2020.2976041

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this article, various characteristics of nanoplate FET were studied based on TCAD simulation for a 3-nm node. The optimum geometry specification was proposed through comparison of RC delay from previous studies. Additionally, the impacts of self-heating effects (SHEs) in the 3-nm node were evaluated in the targeting device because it is expected that highly scaled areas such as channels have a negative effect on the performance due to low heat dissipation. This degradation was verified in a single device and in ring oscillator (RO) operation. pMOS is comparatively stronger than nMOS in terms of SHEs due to wider channel width. In RO operation, the influence of SHEs begins to appear at over 0.65 V through power and speed comparison. Therefore, an operation voltage under 0.65 V can be the optimal voltage to suppress SHEs.

引用

页码：1537 / 1541

页数：5

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