COPPER PLATING PROCESS FOR THROUGH SILICON VIA WITH HIGH ASPECT RATIO IN ADVANCED PACKAGING

被引：0
|
作者：
Huang, Yu Hung [1 ]
Lee, Huei-Huang [1 ]
Hwang, Sheng-Jye [1 ]
Huang, Durn-Yuan
机构：
[1] Natl Cheng Kung Univ, Tainan 70101, Taiwan
来源：
IPACK 2009: PROCEEDINGS OF THE ASME INTERPACK CONFERENCE 2009, VOL 1 | 2010年
关键词：
Through Silicon Via; TSV; Cu RDL; Aspect Ratio; Cu Filling; Void;
D O I：
暂无
中图分类号：
TH [机械、仪表工业];
学科分类号：
0802 ;
摘要：
Through silicon via (TSV) is a technology which allows devices to be connected three-dimensionally. Three dimensional vertical integration using TSV Cu interconnect can greatly increase the packaging density and is one of the most advanced and promising technologies for future IC packaging. However, Cu filling of void free through silicon via with high aspect ratio (AR >= 10) has been a challenge for a long time. In this paper, successful fabrication of void free TSV with very high aspect ratio was demonstrated via electroplating process. Proper equipment and processing conditions for electroplating are required. The same equipment and similar chemicals and process conditions could also be applied to fabricate high quality redistribution line technology (RDL).
引用
收藏
页码：9 / 14
页数：6
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