A Hardware Accelerator for Tracing Garbage Collection

被引:22
作者
Maas, Martin [1 ,2 ]
Asanovic, Krste [1 ]
Kubiatowicz, John [1 ]
机构
[1] Univ Calif Berkeley, Berkeley, CA 94720 USA
[2] Google Brain, Mountain View, CA 94043 USA
来源
2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA) | 2018年
关键词
hardware accelerators; garbage collection; SoCs; language runtime systems; memory management;
D O I
10.1109/ISCA.2018.00022
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A large number of workloads are written in garbage-collected languages. These applications spend up to 10-35% of their CPU cycles on GC, and these numbers increase further for pause-free concurrent collectors. As this amounts to a significant fraction of resources in scenarios ranging from data centers to mobile devices, reducing the cost of GC would improve the efficiency of a wide range of workloads. We propose to decrease these overheads by moving GC into a small hardware accelerator that is located close to the memory controller and performs GC more efficiently than a CPU. We first show a general design of such a GC accelerator and describe how it can be integrated into both stop-the-world and pause-free garbage collectors. We then demonstrate an end-to-end RTL prototype of this design, integrated into a RocketChip RISC-V System-on-Chip (SoC) executing full Java benchmarks within JikesRVM running under Linux on FPGAs. Our prototype performs the mark phase of a tracing GC at 4.2x the performance of an in-order CPU, at just 18.5% the area (an amount equivalent to 64KB of SRAM). By prototyping our design in a real system, we show that our accelerator can be adopted without invasive changes to the SoC, and estimate its performance, area and energy.
引用
收藏
页码:138 / 151
页数:14
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