Compiler managed dynamic instruction placement in a low-power code cache

被引:26
作者
Ravindran, RA [1 ]
Nagarkar, PD [1 ]
Dasika, GS [1 ]
Marsman, ED [1 ]
Senger, RM [1 ]
Mahlke, SA [1 ]
Brown, RB [1 ]
机构
[1] Univ Michigan, Dept EECS, Ann Arbor, MI 48109 USA
来源
CGO 2005: INTERNATIONAL SYMPOSIUM ON CODE GENERATION AND OPTIMIZATION | 2005年
关键词
D O I
10.1109/CGO.2005.13
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Modem embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-pad memories lack the complex tag checking and comparison logic, thereby proving to be efficient in area and power. In this work, we focus on exploiting scratch-pad memories for storing hot code segments within an application. Static placement techniques focus on placing the most frequently executed portions of programs into the scratch-pad. However, static schemes are inherently limited by not allowing the contents of the scratch-pad memory to change at run time. In a large fraction of applications, the instruction memory footprints exceed the scratch-pad memory size, thereby limiting the usefulness of the scratch-pad. We propose a compiler managed dynamic placement algorithm, wherein multiple hot code sequences, or traces, are overlapped with each other in the scratch-pad memory at different points in time during execution. Special copy instructions are provided to copy the traces into the scratch-pad memory at run-time. Using a power estimate, the compiler initially selects the most frequent traces in an application for relocation into the scratch-pad memory. Through iterative code motion and redundancy elimination, copy instructions are inserted in infrequently executed regions of the code. For a 64-byte code cache, the compiler managed dynamic placement achieves an average of 64% energy improvement over the static solution in a low-power embedded microcontroller.
引用
收藏
页码:179 / 190
页数:12
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