The Factored Correlator Model (FCM) is an analytical model for the outputs of a GNSS receiver's correlators. The FCM precludes the need for simulation of the lower-level signal processing stages, significantly increasing simulation speed and considerably decreasing processing and memory requirements, while still keeping a high level of realism. Results for the FCM validation using statistical models (available from previous Galileo studies) and the GRANADA Bit-True Simulator have been presented in the past. However, FCM results have never been compared to those of a real hardware receiver, whose performance is influenced by effects that have not been taken into account in the FCM (as quantization and fixed-point arithmetic, just to name a few). This paper shall present the verification and validation results of the FCM using a real hardware signal processing chain, up to the correlator outputs, implemented on an FPGA, in the scope of ongoing projects. It shall also highlight the new features of the latest GRANADA FCM Blockset release and demonstrate its applicability and value for receiver algorithms design.
