Current mode techniques for sub-pico-ampere circuit design

In this paper we explore the low current limit that standard CMOS technologies offer for current mode based VLSI designs. We show and validate a reliable circuit design technique for current mode signal processing down to fempto-amperes. We will take advantage of specific-current extractors and logarithmic current splitters to obtain on-chip sub-pA currents. Then we will use a special on-chip saw-tooth oscillator to monitor and measure currents down to a few fempto-amps. This way, sub-pA currents are characterized without driving them off-chip, nor requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is implemented that uses a 100 fF capacitor and a 3.5 fA bias current to achieve a cut-off frequency of 0.5 Hz and using an area of 12 x 24.35 mum(2) in a standard 0.35 mum CMOS process. A technique for characterizing noise at these currents is described and verified. Also, temperature dependence of leakage currents is measured as well.