Design of a 6-bit 1GSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications

In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further, a novel layout technique is introduced for compact area. With the clock speed of 1GHz, the ADC achieves an effective resolution bandwidth (ERBW) of 200MHz, while consuming only 60mW of power. The measured INL and DNL are within +/- 0.7LSB, +/- 0.5LSB, respectively. The measured SNDR is 33.64dB, when F-in=100MHz at F-s=1GHz. The active chip occupies an area of 0.27mm(2) in 0.18 mu m CMOS technology.