A Transient-Enhanced Low-Power Standard-Cell-Based Digital LDO

In this article, a transient-enhanced fully synthesizable digital low dropout regulator (FS-DLDO) is proposed for ultra-low-power applications. The FS-DLDO uses a fully synthesizable comparator (FS-Com) to sense load variations. A digital logic controller (D-CTRL) tunes the output voltage (V-O) through a quad-loop architecture. The quad-loop architecture uses short bidirectional shift registers (BSR) to achieve fast-transient response and reduce leakage current. In addition, the FS-DLDO supports freeze-mode to regulate a ripple-free V-O and minimize power consumption at a steady state. To demonstrate this entire design using standard-cells, the P-MOSFET array (PTA) used in traditional digital low dropout regulator (DLDO) is replaced with an array of three-state buffers (TSA). The layout is created using digital design flow in TSMC CMOS 45 nm process, which occupies a 6708 mu m(2) area. For a power supply (V-SUP) range of 0.5-1 V, the FS-DLDO can provide regulated V-O with a 50 mV dropout voltage. At V-SUP = 500 mV and clock frequency (f(CLK)) of 10 MHz, the proposed regulator achieves a transient response time of 0.91 mu s. This prototype achieves a peak current efficiency of 99.90% and produces a ripple-free V-O at a steady state.