共 50 条
[41]
Effect of wire delay on the design of prefix adders in deep-submicron technology
[J].
CONFERENCE RECORD OF THE THIRTY-FOURTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS,
2000,
:1713-1717
[43]
Implimentation and Evaluation of an Efficient Clock Distribution Network for Deep-Submicron Technology
[J].
2015 2ND INTERNATIONAL CONFERENCE ON ELECTRICAL INFORMATION AND COMMUNICATION TECHNOLOGY (EICT),
2015,
:239-242
[44]
MULTILAYER RESIST DRY-ETCHING TECHNOLOGY FOR DEEP-SUBMICRON LITHOGRAPHY
[J].
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B,
1993, 11 (06)
:2284-2287
[45]
Impact of Single-Event Upsets in Deep-Submicron Silicon Technology
[J].
MRS Bulletin,
2003, 28
:117-120
[46]
Output resistance scaling model for deep-submicron cmos buffers for timing performance optimisation
[J].
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION,
2005, 3728
:329-336
[47]
A single photon avalanche diode array fabricated in deep-submicron CMOS technology
[J].
2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS,
2006,
:79-+
[48]
Low power domino logic circuits in deep-submicron technology using CMOS
[J].
ENGINEERING SCIENCE AND TECHNOLOGY-AN INTERNATIONAL JOURNAL-JESTECH,
2018, 21 (04)
:625-638
[49]
Technology-dependent modeling of deep-submicron MOSFET's and ULSI circuits
[J].
SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS,
2001,
:855-860