Pipeline of successive approximation converters with optimum power merit factor

In this paper, we present a low power 12 bit 5 MSPS, successive approximation converter architecture using pipeline technique. The converter consumes 4 mW at the Nyquist rate input with 1.8 V power supply. By combination of pipeline and successive architecture, the entire circuit, simulated at the transistor level in a 0.18 mu CMOS process, achieves a FoM (Figure of Merit) of 0.19 pJ/conversion.