Homo and hetero junctionless tunnel field effect transistors for mixed signal applications: a review

被引:2
作者
Haritha, Karanam [1 ]
Lakshmi, B. [1 ,2 ]
机构
[1] Vellore Inst Technol, Sch Elect Engn, Chennai, Tamil Nadu, India
[2] Vellore Inst Technol, Ctr Nanoelect & VLSI Design, Chennai, Tamil Nadu, India
关键词
Homo JLTFET; Hetero JLTFET; Dual material gate; Metal implant; Silicon-on-nothing; Stacked high-K hetero-gate technology; GBW; TGF; SNM; Heterogeneous nanostructures; ELECTRICAL PERFORMANCE; SENSITIVITY; FET;
D O I
10.1007/s11051-021-05328-9
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
This study presents a systematic review of junctionless tunnel field effect transistor (JLTFET)-based homo- and hetero-based devices/circuits which have gained significant popularity in recent years for their performance. The divergent ranges of JLTFET-based structures are explored, and their DC/AC characteristics are discussed in detail. Basically JLTFET device exploits the advantages of both junctionless FET (JLFET) and tunnel FET (TFET) together to vanquish the major challenges that are faced by contemporary FETs. The hetero JLTFETs studied in this review uses lower band gap materials, silicon and SiXGeX-1 and high band gap material, AlGaAsat source and channel side, respectively. Also dual material gate structure in hetero JLTFET is explored for their performance improvement. Both homo and hetero structures exhibit better performance in terms of DC parameters, subthreshold slope (SS), ON-current, OFF-current and electron tunnelling rate, whereas AC parameters include unity gain cut-off frequency (f(t)), maximum oscillation frequency (f(max)), gain bandwidth product (GBW), transconductance generation factor (TGF) and delay. The silicon-on-nothing (SON) technology-based JLTFET is studied for the performance improvement by using different dielectric materials. With respect to circuit-related study, JLTFET uses SiGeN + pocket under the gate region which act as an inverter circuit with good transient and voltage transfer characteristics (VTC). For memory circuits like SRAM, JLTFET shows better performance in terms of hold static noise margin (SNM), read SNM and write SNM.
引用
收藏
页数:19
相关论文
共 23 条
[1]   Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement [J].
Aghandeh, Hadi ;
Ziabari, Seyed Ali Sedigh .
SUPERLATTICES AND MICROSTRUCTURES, 2017, 111 :103-114
[2]   Modeling CNTFET Performance Variation Due to Spatial Distribution of Carbon Nanotubes [J].
Ahmed, Zubair ;
Zhang, Lining ;
Sarfraz, Khawar ;
Chan, Mansun .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (09) :3776-3781
[3]   Effect of ITC's on linearity and distortion performance of Junctionless tunnel field effect transistor [J].
Awadhiya, Bhaskar ;
Pandey, Sunil ;
Nigam, Kaushal ;
Kondekar, Pravin N. .
SUPERLATTICES AND MICROSTRUCTURES, 2017, 111 :293-301
[4]   Optimisation of pocket doped junctionless TFET and its application in digital inverter [J].
Devi, Wangkheirakpam Vandana ;
Bhowmick, Brinda .
MICRO & NANO LETTERS, 2019, 14 (01) :69-73
[5]   A New Simulation Approach of Transient Response to Enhance the Selectivity and Sensitivity in Tunneling Field Effect Transistor-Based Biosensor [J].
Dwivedi, Praveen ;
Singh, Rohit ;
Sengar, Brajendra Singh ;
Kumar, Amitesh ;
Garg, Vivek .
IEEE SENSORS JOURNAL, 2021, 21 (03) :3201-3209
[6]   Junctionless Tunnel Field Effect Transistor [J].
Ghosh, Bahniman ;
Akram, Mohammad Waseem .
IEEE ELECTRON DEVICE LETTERS, 2013, 34 (05) :584-586
[7]   Effect of Interface Trap Charges on Performance Variation of Heterogeneous Gate Dielectric Junctionless-TFET [J].
Gupta, Sarthak ;
Nigam, Kaushal ;
Pandey, Sunil ;
Sharma, Dheeraj ;
Kondekar, Pravin N. .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (11) :4731-4737
[8]   Silicon-On-Nothing Electrostatically Doped Junctionless Tunnel Field Effect Transistor (SON-ED-JLTFET): A Short Channel Effect Resilient Design [J].
Kaity, Aishwarya ;
Singh, Sangeeta ;
Kondekar, P. N. .
SILICON, 2021, 13 (01) :9-23
[9]   Influence of Process Variations on the Electrical Performance of SiC Power MOSFETs [J].
Mueting, Johanna ;
Natzke, Philipp ;
Tsibizov, Alexander ;
Grossner, Ulrike .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 68 (01) :230-235
[10]   A new approach for design and investigation of junction-less tunnel FET using electrically doped mechanism [J].
Nigam, Kaushal ;
Kondekar, Pravin ;
Sharma, Dheeraj ;
Raad, Bhagwan Ram .
SUPERLATTICES AND MICROSTRUCTURES, 2016, 98 :1-7