Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process

被引：3

作者：

Wang, Yuan ^{[1
]}

Lu, Guangyi ^{[1
]}

Guo, Haibing ^{[1
]}

Cao, Jian ^{[1
]}

Jia, Song ^{[1
]}

Zhang, Xing ^{[1
]}

机构：

[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China

来源：

SCIENCE CHINA-INFORMATION SCIENCES | 2016年 / 59卷 / 04期

关键词：

electrostatic discharge (ESD); power-rail clamp circuit; transmission line pulse (TLP); current mirror; mis-triggering; ESD PROTECTION; SUPPLY CLAMP; DESIGN;

D O I：

10.1007/s11432-015-5398-3

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel, area-efficient transient power-rail electrostatic discharge (ESD) clamp circuit is proposed in this work. Current-mirror capacitors are used to reduce the layout area. Logic threshold voltages of inverters are modified to ensure a fully active on-state for the clamp device in ESD conditions. The proposed circuit reduces the layout area by about 56% compared with a circuit without current-mirror capacitors. Transmission line pulse (TLP) test results based on a 65-nm CMOS process demonstrate that the proposed circuit is an efficient on-chip ESD protection scheme for this process. In addition, the proposed circuit achieves a good immunity to mis-triggering with respect to fast power-up transitions.

引用

页数：9

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