An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop

Availability of a reliable ON-chip oscillator can secure a system-on-chip (SoC) against physical clock attacks by enabling applications such as boot-up using ON-chip oscillator and hardware clock monitors. This article proposes a frequency-error feedback (FEF) loop-based relaxation oscillator for such applications. It suppresses the low-frequency noise and improves the time interval error (TIE) without degrading the period jitter. It also stabilizes the oscillator against supply and temperature variations. A 77-MHz oscillator prototype is fabricated in a commercial 5-nm FinFET process. Operating from 0.9-V digital and 1.2-V analog supplies, the prototype consumes a total of 0.84 mW and occupies an area of 0.0152 mm(2). It achieves a TIE of 3 ns over 10 K cycles which is 3x better than an oscillator without an FEF loop. Chip samples are picked from four wafer split lots. The worst case frequency variation measured from 16 samples is 1-0.25% across an analog supply change of 1.1-1.35 V, while a variation of +/- 0.3% is measured over -40 to 125 degrees C temperature from eight samples.