Polar Compiler: Auto-Generator of Hardware Architectures for Polar Encoders

Polar codes have been standardized for enhanced mobile broadband (eMBB) control channels and been considered by other applications. Though there are lots of works on polar encoder implementations, the manual design is laborious regarding various application requirements. This paper devotes itself in proposing a compiler to automatically generate target polar encoders in Verilog HDL files, given code length, parallelism level, and stage number. This compiler is based on uniform formula representations of pipelined or stage-folded polar encoders. Thanks to the compiler, designers have been freed from manual design and enabled to conduct hardware optimization in design space with constraints on area, latency, power, or throughput. Implementation results show that polar encoders generated by the compiler are more efficient than the state-of-the-art ones in terms of area and energy.