A guaranteed-throughput switch for network-on-chip

被引：9

作者：

Liu, J ^{[1
]}

Zheng, LR ^{[1
]}

Tenhunen, H ^{[1
]}

机构：

[1] Royal Inst Technol, LECS, SE-16440 Stockholm, Sweden

来源：

INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/ISSOC.2003.1267710

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Today's systems on a chip (SoC) contain numerous complex functional blocks integrated by an elaborate network of interconnects and buses. As systems grow in complexity, the on-chip interconnect network is expected to become critical for overall system-level metrics, such as performance, power consumption, reliability ets. However, present day's dedicated channels and shared buses do not scale and therefore do not meet these requirements. The emerging Network-on-Chip approach, based on on-chip communication network, might solve the problems [3]. In this paper, a guaranteed-throughput switch designed for NoC is described. This switch provides in-order delivery and supports multicast operation. It is implemented with random access memory at the input and output. The input and output are then connected by a fully connected interconnect network.

引用

页码：31 / 34

页数：4

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