Design of a Low Power Adiabatic Logic based Johnson Counter

被引：0

作者：

Sharma, Himanshi ^{[1
]}

Singh, Rajan ^{[1
]}

机构：

[1] Noida Inst Engn Technol, ECE, Greater Noida, India

来源：

2015 INTERNATIONAL CONFERENCE ON GREEN COMPUTING AND INTERNET OF THINGS (ICGCIOT) | 2015年

关键词：

CPAL; Adiabatic Logic; Johnson Counter; Leakage Current;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper provides a deep insight to the design of an adiabatic Johnson Counter which consumes low power and delivers high performance. For achieving low power dissipation in circuits the Complementary Pass Transistor Adiabatic Logic (CPAL) is used to design the flip flops. The design of Johnson counter has been simulated and verified. The Tanner EDA tool has been used to simulate all the circuits with 90nm technology. Working within the Mhz frequency band, the proposed design has shown lower power dissipation.

引用

页码：270 / 274

页数：5

共 17 条

[1]

Agarwal A, 2004, DES AUT CON, P6

[2] LOW-POWER CMOS DIGITAL DESIGN [J].

CHANDRAKASAN, AP ;

SHENG, S ;

BRODERSEN, RW .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) :473-484

[3]

Chauhan Manish, 2015, INT J ELECT ELECT EN, V07

[4]

Denker J. S., 1994, 1994 IEEE Symposium on Low Power Electronics. Digest of Technical Papers (Cat. No.94TH0669-2), P94, DOI 10.1109/LPE.1994.573218

[5]

Gavaskar Reddy Sunil, 2011, ARXIV11101549

[6]

Hu JP, 2012, PRZ ELEKTROTECHNICZN, V88, P277

[7]

HU JP, 2009, MICROELECTRONICS ELE, P456

[8]

INDERMAUER T., 2002, IEEE S LOW POW EL SA, P102

[9]

Jianping Hu, 2005, 2005 48th IEEE International Midwest Symposium on Circuits and Systems (IEEE Cat. No. 05CH37691), P1398

[10]

Koller J. G., 2005, 4 GREAT LAK S VLSI C

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