The NAPA Adaptive Processing Architecture

被引：36

作者：

Rupp, CR ^{[1
]}

Landguth, M ^{[1
]}

Garverick, T ^{[1
]}

Gomersall, E ^{[1
]}

Holt, H ^{[1
]}

Arnold, JM ^{[1
]}

Gokhale, M ^{[1
]}

机构：

[1] Natl Semicond Corp, Santa Clara, CA 95051 USA

来源：

IEEE SYMPOSIUM ON FPGAS FOR CUSTOM COMPUTING MACHINES, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/FPGA.1998.707878

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The National Adaptive Processing Architecture (NAPA) is a major effort to integrate the resources needed to develop teraops class computing systems based on the principles of adaptive computing. The primary goals for this effort include: (1) the development of an example NAPA component which achieves an order of magnitude cost/performance improvement compared to traditional FPCA based systems, (2) the creation of a rich but effective application development environment for NAPA systems based on the ideas of compile time functional partitioning and (3) significantly improve the base infrastructure for effective research in reconfigurable computing. This paper emphasizes the technical aspects of the architecture to achieve the first goal while illustrating key architectural concepts motivated by the second and third goals.

引用

页码：28 / 37

页数：10