PRECISIO RF front-end

被引:0
|
作者
Tarazona, Luis [1 ,2 ]
Bavaro, Michele [2 ]
机构
[1] De Montfort Univ, Fac Technol, Dept Engn, Leicester LE1 9BH, Leics, England
[2] Nottingham Sci Ltd, Nottingham NG2 1RT, England
来源
2010 5TH ESA WORKSHOP ON SATELLITE NAVIGATION TECHNOLOGIES AND EUROPEAN WORKSHOP ON GNSS SIGNALS AND SIGNAL PROCESSING (NAVITEC) | 2010年
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暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
There is certainly a growing interest for the biggest countries in the world on having their own navigation system, which will result in many satellites and signals available in the near future. Given this fact, it starts making sense to design a multi-constellation GNSS receiver with an architecture that combines simplicity and flexibility. When building the front-end of the receiver, the well established heterodyne solution is not readily scalable. The not-so-new herein proposed approach is well known as Direct Bandpass Sampling (DBS). Indeed for more than ten years it has been cited in publications where the aprroach has been used as a research topic. More recently the approach is experiencing a second exciting boom of interest. In this paper we describe the PRECISIO GNSS front-end, from RF, analog, and digital point of view. The object of our study is to come up with a very much product-oriented prototype, with its implied performance/costs/for-factor trade-offs. The RF section is most critical in a DBS design because the amount of noise folding on the band of interest depends on the quality of the filters before the ADC. The filtering is made using bespoke dual-band filters, which constitute the most expensive components of the design. The clock synthesizer on board delivers the lowest phase noise in the market. The filtered GNSS signals are sampled at 540 MHz using a low cost device from NSC. The digital streams are processed using polyphase techniques for decimation, downconversion and filtering, reducing the FPGA speed and power requirements. The digital filtering is done with multiplier-less FIR structures. These architecture features allow the design to target a low-cost FPGA device.
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页数:4
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