Dynamically scheduling the trace produced during program execution into VLIW instructions

被引：1

作者：

de Souza, AF ^{[1
]}

Rounce, P ^{[1
]}

机构：

[1] Univ London Univ Coll, Dept Comp Sci, London WC1E 6BT, England

来源：

IPPS/SPDP 1999: 13TH INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM & 10TH SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/IPPS.1999.760471

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

VLIW machines possibly provide the most direct way to exploit instruction level parallelism; however, they cannot be used to emulate current general-purpose instruction set architectures. Programs scheduled for a particular implementation of a VLIW model cannot be guaranteed to be binary compatible with other implementations of the sa,ne machine model with different number of functional-units. This paper describes an architecture, named dynamically trace scheduled VLIW (DTSVLIW), which can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility. Some preliminary performance measurements of the DTSVLIW, obtained with an execution-driven simulator running the SPECint95 benchmark suite, are also presented.

引用

页码：248 / 257

页数：10

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