AIMR: An Adaptive Page Management Policy for Hybrid Memory Architecture with NVM and DRAM

被引:6
作者
Sun, Zhiwen [1 ]
Jia, Zhiping [1 ]
Cai, Xiaojun [1 ]
Zhang, Zhiyong [1 ]
Ju, Lei [1 ]
机构
[1] Shandong Univ, Sch Comp Sci & Technol, Jinan, Lixia, Peoples R China
来源
2015 IEEE 17TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2015 IEEE 7TH INTERNATIONAL SYMPOSIUM ON CYBERSPACE SAFETY AND SECURITY, AND 2015 IEEE 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (ICESS) | 2015年
关键词
PHASE-CHANGE MEMORY; ENERGY-EFFICIENT;
D O I
10.1109/HPCC-CSS-ICESS.2015.179
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
The last few years have witnessed the emergence of Non-Volatile Memories (NVMs), which are actively pursued as scalable substitutes for traditional DRAM-based main memory due to higher scalability and lower leakage power. However, current NVM technologies also exhibit potential drawbacks including lower endurance, higher dynamic power, and longer write latency. Recent studies show that hybrid memory architectures involving NVM and DRAM are able to effectively utilize the merits of both memory devices. However, allocating write-intensive pages to NVM can still greatly impeding the performance of the overall memory system. In this paper, we provide an adaptive page management policy called AIMR (Adaptive page Insertion, Migration, and Replacement) for hybrid memory architecture. The main objective of our scheme is to ensure DRAM absorbs most memory writes while maintaining a high performance of the overall system. Specifically, we use both "recency" and "frequency" features to estimate the future memory access patterns and then carefully insert, migrate, and replace pages in the hybrid memory without setting any additional user-defined parameters. Experimental results show that AIMR can achieve average NVM write count, memory access latency, and memory energy consumption reduction by 19.3%, 45.8% and 27.8%, respectively compared with the existing page management policies under hybrid memory architecture.
引用
收藏
页码:284 / 289
页数:6
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