QED Post-Silicon Validation and Debug: Frequently Asked Questions

During post-silicon validation and debug, one or more manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). According to several industrial reports, the costs of post-silicon validation and debug are rising faster than design costs. Hence, new techniques are essential to reverse this trend. QED, an acronym for Quick Error Detection, is such a technique that effectively overcomes several post-silicon validation and debug challenges. QED systematically creates a wide variety of validation tests to quickly detect bugs, not only inside processor cores, but also inside uncore components (i.e., components in an SoC that are neither processor cores nor co-processors) of multi-core SoCs. In this paper, we present a brief overview of QED through a series of frequently asked questions.