Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity

被引：0

作者：

Tang, Kai-Neng ^{[1
]}

Liao, Seian-Feng ^{[1
]}

Ker, Ming-Dou ^{[1
]}

Chiou, Hwa-Chyi ^{[2
]}

Huang, Yeh-Jen ^{[2
]}

Tsai, Chun-Chien ^{[2
]}

Jou, Yeh-Ning ^{[2
]}

Lin, Geeng-Lih ^{[2
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu, Taiwan

[2] Vanguard Int Semicond Corp, Hsinchu, Taiwan

来源：

2015 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC) | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Electrostatic discharge (ESD) and latchup are important reliability issues to the CMOS integrated circuits in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS has been verified to sustain a high ESD level with high holding voltage in a 0.25-mu m BCD process. Stacked devices in different configuration were also investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.

引用

页码：325 / 328

页数：4

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