Bridging the processor-memory performance gap with 3D IC technology

被引:179
作者
Liu, CC [1 ]
Ganusov, I [1 ]
Burtscher, M [1 ]
Tiwari, S [1 ]
机构
[1] Cornell Univ, Sch Elect & Comp Engn, Ithaca, NY 14853 USA
来源
IEEE DESIGN & TEST OF COMPUTERS | 2005年 / 22卷 / 06期
关键词
D O I
10.1109/MDT.2005.134
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Bringing the memory close to the processor is obviously a good idea for reducing latency, but the memory is not a monolith: It includes submodules, and their arrangement determines the effectiveness of using 3D technology. The authors look at various scenarios for arranging the CPU relative to the memory modules and provide a quantitative comparison. © 2005 IEEE.
引用
收藏
页码:556 / 564
页数:9
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