A Novel Page Caching Policy for PCM and DRAM of Hybrid Memory Architecture

被引:5
作者
Cai, Xiaojun [1 ]
Ju, Lei [1 ]
Zhao, Mengying [1 ]
Sun, Zhiwen [1 ]
Jia, Zhiping [1 ]
机构
[1] Shandong Univ, Sch Comp Sci & Technol, Jinan, Shandong, Peoples R China
来源
2016 13TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (ICESS) - PROCEEDINGS | 2016年
基金
中国国家自然科学基金;
关键词
DRAM; PCM; Hybrid Memory architecture; CLOCK-HM; Page caching; PHASE-CHANGE MEMORY; ALGORITHM;
D O I
10.1109/ICESS.2016.17
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Recently, Phase Change Memory (PCM), one of non-volatile memory (NVM), has provided a great chance to improve the performance of memory subsystem. In this paper, we propose a novel page caching policy for PCM and DRAM hybrid memory architecture called CLOCK-HM (CLOCK for page cache in Hybrid Memory architecture). Through two lists and some flag bits, it tries to minimize the write access occurrences on PCM and the migrations between DRAM and PCM, while maintaining a high page hit ratio. Simulation results show that CLOCK-HM maintains a high hit ratio as similar as CLOCK algorithm. Importantly, compared to other algorithms, CLOCK-HM significantly reduces the number of write operations on PCM and the migrations between PCM and DRAM.
引用
收藏
页码:67 / 73
页数:7
相关论文
共 18 条
[1]  
Bansal S, 2004, USENIX ASSOCIATION PROCEEDINGS OF THE 3RD USENIX CONFERENCE ON FILE AND STORAGE TECHNOLOGIES, P187
[2]  
Dhiman G, 2009, DES AUT CON, P664
[3]   Hybrid Checkpointing Using Emerging Nonvolatile Memories for Future Exascale Systems [J].
Dong, Xiangyu ;
Xie, Yuan ;
Muralimanohar, Naveen ;
Jouppi, Norman P. .
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2011, 8 (02)
[4]   FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory [J].
Jiang, Lei ;
Zhang, Youtao ;
Childers, Bruce R. ;
Yang, Jun .
2012 IEEE/ACM 45TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO-45), 2012, :1-12
[5]  
Lee BC, 2009, CONF PROC INT SYMP C, P2, DOI 10.1145/1555815.1555758
[6]  
Lee D, 1999, PERFORMANCE EVALUATION REVIEW, SPECIAL ISSUE, VOL 27 NO 1, JUNE 1999, P134, DOI 10.1145/301464.301487
[7]   CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures [J].
Lee, Soyoon ;
Bahn, Hyokyung ;
Noh, Sam H. .
IEEE TRANSACTIONS ON COMPUTERS, 2014, 63 (09) :2187-2200
[8]  
Liu JM, 2012, CONF PROC INT SYMP C, P1, DOI 10.1109/ISCA.2012.6237001
[9]  
Mittal Sparsh., 2012, Int. J. High Perform. Syst. Architect., V4, P110
[10]  
Papandreou N., 2011, IEEE International Memory Workshop, P1, DOI DOI 10.1109/IMW.2011.5873231