Design Techniques for Ultra Low-Power Phase-Locked Loops

被引：0
|
作者：
Park, Dongmin [1 ]
Cho, SeongHwan [1 ]
机构：
[1] Korea Adv Inst Sci & Technol, Dept EE, Taejon, South Korea
来源：
2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2011年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Ultra-low power frequency synthesizers resilient to environmental variations are desired in various wireless microsensor applications where power consumption and reliability are important performance metrics. This paper reviews the design techniques for a ultra-low power PLLs employing low-supply voltage and charge recycling techniques. Design challenges such as minimizing sensitivity to environmental variations are addressed for low-voltage and charge-recycling operation, which include adaptive body-biasing and implicit negative feedback DCDC conversion.
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页数：4
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