1/f Noise Sources in Dual-Gated Indium Arsenide Nanowire Transistors

被引:14
作者
Delker, Collin J. [1 ,2 ]
Kim, Seongmin [1 ,2 ]
Borg, Mattias [3 ]
Wernersson, Lars-Erik [3 ]
Janes, David B. [1 ,2 ]
机构
[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA
[2] Purdue Univ, Birck Nanotechnol Ctr, W Lafayette, IN 47907 USA
[3] Lund Univ, Dept Elect & Informat Technol, S-22100 Lund, Sweden
基金
美国国家科学基金会;
关键词
Indium Arsenide; low-frequency noise; nanowire FETs; DEVICES;
D O I
10.1109/TED.2012.2194150
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
1/f noise is studied in dual-gated InAs nanowire transistors consisting of an omega top gate with high-k atomic layer deposited dielectric and silicon dioxide to substrate back gate. Noise spectra at varying gate bias combinations are compared from devices with differing top-gate lengths to separate the noise contributions of the top-gated channel from the ungated access portion, including the metal-nanowire contacts. For a given device geometry, it is possible to bias the device into four different regimes where the resistance and the noise amplitude can each be independently dominated by either the channel or the access/contact regions. When the device is fully in the on state, the access/contact regions dominate both resistance and noise. When the device is operating near or below threshold, the channel dominates resistance and noise. For the lowest amount of overall 1/f noise, most of the nanowire should be covered by the top gate, minimizing the access region length.
引用
收藏
页码:1980 / 1987
页数:8
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