A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis

被引:4
作者
Damnjanovic, Vukan D. [1 ]
Petrovic, Marija L.
Milovanovic, Vladimir M.
机构
[1] Univ Kragujevac, Fac Engn, Sestre Janjic 6, Kragujevac, Serbia
来源
2021 24TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS) | 2021年
关键词
Numerically controlled oscillator; direct digital synthesizer; Chisel hardware design language; design generator;
D O I
10.1109/DDECS52668.2021.9417063
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Numerically controlled oscillators (NCOs) as part of direct digital synthesizers (DDS) are important components in many digital communication subsystems, such as various digital modulation and demodulation schemes, up and down converters, radar, sonar and laser appliances, etc. The vast number of their beneficial characteristics is what makes NCOs so widely used. Taking this into account, a parameterizable generator of numerically controlled oscillators is implemented using Chisel hardware design language. The proposed generator provides a broad range of parameter configurations, such as input and output data types and widths, the number of different output samples, optional use of spur-reducing techniques or different input interfaces, just to name a few. Numerous generated instances have been tested in software simulations and mapped and tested onto a commercial FPGA platform. Obtained results proved that a generator of this kind can legitimately be compared with custom designed NCO modules, both in terms of performance and resource utilization.
引用
收藏
页码:141 / 144
页数:4
相关论文
共 10 条
  • [1] Bachrach J, 2012, DES AUT CON, P1212
  • [2] Damnjanovic V., CHISEL GENERATOR NUM
  • [3] Kroupa V. F., 1999, DIRECT DIGITAL FREQU
  • [4] Lattice Semiconductor Corporation, 2010, IPUG36025 LATT SEM C IPUG36025 LATT SEM C
  • [5] Lee Y, 2016, IEEE MICRO, V36, P8, DOI 10.1109/MM.2016.11
  • [6] Rigge P., 2018, P 2 WORKSH COMP ARCH P 2 WORKSH COMP ARCH
  • [7] Volder Jack, 1959, W JOINT COMPUTER C, P257
  • [8] Wang A., 2018, 55 ACM ESDA IEEE DES 55 ACM ESDA IEEE DES
  • [9] Weidong Li, 1993, [1993] Proceedings The European Conference on Design Automation with the European Event in ASIC Design, P217, DOI 10.1109/EDAC.1993.386473
  • [10] Xilinx, 2021, DDS COMP V6 0 LOGICO DDS COMP V6 0 LOGICO