Low-Cost Nanostructures from Nanoparticle-Assisted Large-Scale Lithography Significantly Enhance Thermal Energy Transport across Solid Interfaces

被引:28
作者
Lee, Eungkyu [1 ]
Menumerov, Eredzhep [1 ]
Hughes, Robert A. [1 ]
Neretina, Svetlana [1 ,2 ]
Luo, Tengfei [1 ,2 ]
机构
[1] Univ Notre Dame, Dept Aerosp & Mech Engn, Notre Dame, IN 46556 USA
[2] Univ Notre Dame, Ctr Sustainable Energy Notre Dame ND Energy, Notre Dame, IN 46556 USA
基金
美国国家科学基金会;
关键词
thermal management; thermal boundary resistance; Au nanoparticles; low-cost lithography; thermal transport enhancement; nanostructures; CONDUCTANCE; DYNAMICS;
D O I
10.1021/acsami.8b08180
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
Enhancing thermal energy transport across solid interfaces is of critical importance to a wide variety of applications ranging from energy systems and lighting devices to electronics. Nanoscale surface roughness is usually considered detrimental to interfacial thermal transport because of its role in phonon scattering. In this study, however, we demonstrate significant thermal conductance enhancements across metal-semiconductor interfaces by as much as 90% higher than that of the planar interfaces using engineered nanostructures fabricated by Au nanoparticle (NP)-assisted lithography, where self-assembled Au NPs are used as an efficient etching mask to pattern solid substrates over large surface areas. The enlarged interfacial contact area due to the presence of nanostructures is the main reason for the significantly enhanced thermal transport. It is further demonstrated that the conductance can be systematically tuned over a wide range through the use of the Au NP self-assembly process that is regulated by a sacrificial Sb layer whose thickness determines the size and density of the nanostructures produced. This strategy is tested on two technologically important semiconductors, Si and GaN, and their interfacial thermal conductance with Al being measured using the time-domain thermoreflectance technique. Moreover, the nanostructured interfaces can maintain the enhanced conductance for a temperature range of 30-110 degrees C-the operating temperatures commonly experienced by energy, lighting, and electronic devices. Our results could provide a wafer-scale and low-cost strategy for improving the thermal management of these devices.
引用
收藏
页码:34690 / 34698
页数:9
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