Sizing and characterization of leakage-control cells for layout-aware distributed power-gating

被引：6

作者：

Babighian, P ^{[1
]}

Benini, L ^{[1
]}

Macii, E ^{[1
]}

机构：

[1] Politecn Torino, I-10129 Turin, Italy

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/DATE.2004.1268947

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a methodology for sleep transistor sizing for usage in a novel, single-threshold leakage cut-off approach, where power gating cells are distributed row-by-row in a fully placed circuit. Sizing equations are obtained by performing SPICE simulations for a 130nm technology. Furthermore, the layout of a test case is considered and power and delay values are extracted-in order to demonstrate the practical impact of our solution.

引用

页码：720 / 721

页数：2