共 9 条
[1]
[Anonymous], 2001, INTRO ALGORITHMS
[2]
KODAVARTI R, 1993, P VLSI TEST S
[3]
Techniques for transient fault sensitivity analysis and reduction in VLSI circuits
[J].
18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS,
2003,
:597-604
[4]
Mohanram K, 2003, INT TEST CONF P, P893, DOI 10.1109/TEST.2003.1271075
[5]
Mukherjee SS, 2003, 36TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, P29
[6]
A systematic approach to SER estimation and solutions
[J].
41ST ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM,
2003,
:60-70
[9]
Shivakumar P., 2002, P INT C DEP SYST NET