VHDL Procedure for Combinational Divider

被引：0
|
作者：
Fedra, Zbynek [1 ]
Kolouch, Jaromir [1 ]
机构：
[1] Brno Univ Technol, Brno, Czech Republic
来源：
2011 34TH INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS AND SIGNAL PROCESSING (TSP) | 2011年
关键词：
divider; FPGA; implementation; procedure; static timing analysis; VHDL;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices - amount of FPGA resources used and maximum delay, are given in tables.
引用
收藏
页码：469 / 471
页数：3
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