A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS

被引：37

作者：

Youssef, Michael ^{[1
,2
]}

Zolfaghari, Alireza ^{[1
]}

Mohammadi, Behnam ^{[1
]}

Darabi, Hooman ^{[1
]}

Abidi, Asad A. ^{[2
]}

机构：

[1] Broadcom Corp, Irvine, CA 92617 USA

[2] Univ Calif Los Angeles, Los Angeles, CA 90095 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2011年 / 46卷 / 12期

关键词：

CMOS; low-power; multimode; polar; transmitter; two-point injection PLL; VCO linearization; WCDMA; DIGITALLY-CONTROLLED OSCILLATOR; FRACTIONAL-N SYNTHESIZER; DELTA-SIGMA-MODULATION; ENVELOPE; DESIGN;

D O I：

10.1109/JSSC.2011.2166432

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-power, multimode polar transmitter based on a two-point injection PLL with a linearized VCO is implemented in 65-nm CMOS technology. A wideband feedback loop, nested inside the PLL with negligible area and power consumption over-head, linearizes and accurately controls the tuning characteristic of the VCO, which is a key requirement when directly modulating the oscillator. Differential delay between AM-PM paths is predictable and is self-calibrated. In WCDMA mode, the transmitter achieves -42/58-dBc ACLR at 5/10-MHz offsets, -159-dBc/Hz receive band noise, and 2.9% EVM at 0-dBm output power while drawing 40-mA from a 3.6-V battery. The DG09 battery current is 25-mA based on a typical PA gain profile and the chip active area is 0.7-mm(2).

引用

页码：3061 / 3074

页数：14