Mitigating the Passing Word Line Induced Soft Errors in Saddle Fin DRAM

In this article, a novel technique using the work-function (WF) engineering of passing word line (PWL) has been proposed to mitigate zero-failure in Saddle-Fin-Recessed-Channel-Access-Transistor (S-RCAT). The zero-failure caused by the hammered access [i.e., row hammer (RH)] of PWL is shown to be due to the interference between the PWL and the adjacent storage node (SN). We propose a localized introduction of a high WF PWL to minimize the interference between the PWL and the SN significantly. Using TCAD 3-D process simulations, we analyze the mechanism of PWL hammer-induced zero-failure. We show that a high WF PWL reduces the electron current density by 92% near the shallow-trench-isolation (STI) during the accessing of PWL. The lesser electron density near STI isolates the SN potential to rise due to the hammered access of PWL, which results in the improvement of 77% in zero-failure mitigation. The introduction of high WF PWL does not have any substantial effect on active access transistor characteristics ( ${I}_{{\mathrm {ON}}}$ , SS, and ${V}_{T}$ ). The results obtained in this article demonstrate the potential of using localized high WF PWL in S-RCAT to mitigate the zero-failure in the future dynamic-random-access-memory (DRAM) technology.