A compact 3-D VLSI classifier using bagging MP threshold network ensembles

A bagging ensemble consists of a set of classifiers trained independently and-combined by a majority vote. Such a combination improves generalization performance but can require. large amounts of memory and computation, a serious drawback for addressing portable real-time pattern recognition applications. We report here a compact three-dimensional (3-D) multiprecision very large-scale integration (VLSI) implementation of a bagging ensemble. In our circuit, individual classifiers are decision trees implemented as threshold networks-one layer of threshold logic units (TLUs) followed by combinatorial logic functions. The hardware was fabricated using 0.7-mum CMOS technology and packaged using MCM-V micro-packaging technology. The 3-D chip implements up to 192 TLUs operating at a speed of up to 48GCPPS and implemented in a volume of (w x L x h) = (2 x 2 x 0.7) cm(3). The 3-D circuit features a high level of programmability and flexibility offering the possibility to make an efficient use of the hardware resources in order to reduce the power consumption. Successful operation of the 3-D chip for various precisions and ensemble sizes is demonstrated through an electronic nose application.