Design, characterization and signal integrity analysis of a 2.5 Gb/s high-speed serial interface for automotive applications overarching the chip/PCB wall

被引：0

作者：

Cossettini, A. ^{[1
]}

Cristofoli, A. ^{[1
,2
]}

Grollitsch, W. ^{[2
]}

Alves, L. ^{[2
]}

Nonis, R. ^{[2
]}

Della Ricca, L. ^{[2
]}

Palestri, P. ^{[1
]}

Selmi, L. ^{[1
]}

机构：

[1] Univ Udine, Udine, Italy

[2] Infineon Technol, Villach, Austria

来源：

2015 IEEE 1ST INTERNATIONAL FORUM ON RESEARCH AND TECHNOLOGIES FOR SOCIETY AND INDUSTRY (RTSI 2015) PROCEEDINGS | 2015年

关键词：

Automotive; eye diagram; high-speed serial link; jitter; source series terminated (SST) driver; NM CMOS TECHNOLOGY; 90-NM CMOS; TRANSMITTER; TRANSCEIVER; LINK; DFE; 4-TAP; FFE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 2.5 Gb/s high-speed serial transmitter for automotive applications has been designed and a circuit/package/board integrated simulation procedure has been set up, enabling the co-design of High-Speed-Serial Interfaces. This simulation methodology employs transistor level models of the transmitter combined with physical-based models of the transmission channel, thus no simplified behavioral models are needed. Model/hardware correlation is reported, including eye closure and jitter effects. Good mutual agreement is found between experiments and simulations.

引用

页数：5

共 44 条

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