共 22 条
[2]
Fully digital AER convolution chip for vision processing
[J].
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10,
2008,
:652-655
[5]
Davison Andrew P, 2008, Front Neuroinform, V2, P11, DOI 10.3389/neuro.11.011.2008
[6]
A serial communication infrastructure for multi-chip address event systems
[J].
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10,
2008,
:648-651
[7]
Furber S., 2012, Computers, IEEE Transactions on, VPP, P1
[8]
Galluppi F, 2010, LECT NOTES COMPUT SC, V6443, P58, DOI 10.1007/978-3-642-17537-4_8
[9]
A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity
[J].
IEEE TRANSACTIONS ON NEURAL NETWORKS,
2006, 17 (01)
:211-221
[10]
SpiNNaker: Mapping Neural Networks onto a Massively-Parallel Chip Multiprocessor
[J].
2008 IEEE INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1-8,
2008,
:2849-2856