High data-rate readout logic design of a 512 x 1024 pixel array dedicated for CEPC vertex detector

CMOS Pixel Sensors (CPS) are attractive for CEPC vertex detector construction due to its high granularity, high speed, low material budgets, low power and potential high radiation tolerance. The characteristics of the sensing diode and the readout architecture were studied using several chips with small-scaled pixel array for CEPC vertex detector. This paper will study the design of a high data-rate readout logic design of a 512 x 1024 pixel array. For the innermost layer of CEPC vertex detector, the hit pixel frequency is near 120 MHz, which is several times higher than the design requirements of ALPIDE for ALICE vertex detector. Based on the hit-driven readout scheme in the pixel array of ALPIDE and FEI3, we propose a new peripheral readout logic design. All the double columns of pixels are read out in parallel and a fast readout architecrue of 512 double columns is realized. Meanwhile, a real-time data compression and a trigger-mode operation are supported to reduce the data output. The simulation results indicate the pixel hit frequency in average of 120 MHz can be processed with readout time of 50 ns per pixel and of less than 500 ns per double column of pixels. The layout area is 25.68 x 1.13 mm(2). The power density in trigger mode and in triggerless mode are estimated as 25 similar to 30 mW/cm(2) and 35 similar to 45 mW/cm(2) respectively.