CAPACITOR LESS DRAM CELL DESIGN FOR HIGH PERFORMANCE EMBEDDED SYSTEM

被引：0

作者：

Asthana, Prateek ^{[1
]}

Mangesh, Sangeeta ^{[1
]}

机构：

[1] JSS Acad Tech Educ, Dept Elect & Commun, Noida, India

来源：

2014 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI) | 2014年

关键词：

Low Power; TANNER EDA; DRAM; 3T1D DRAM; Memory Design;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this paper average power consumption and timing parameter i.e. read access time, write access time and retention time comparison of 3T1D DRAM is carried out. These analyses are carried out on 32nm scale. This DRAM cell is used in high performance embedded system. A technique is being used in the paper to improve average power consumption and read access time for 3T1D DRAM to make it more comparable to the SRAM 6T. A circuit to improve the average power consumption and the read access time of the 3T1D cell are analyzed. These circuits are analyzed on TANNER EDA. Circuits are designed on SEDIT and simulated on TSPICE.

引用

页码：554 / 559

页数：6