VLSI implementation of the motion estimator with two-dimensional data-reuse

被引：5

作者：

Lai, YK

Lai, YL

Liu, YC

Wu, PC

Chen, LG

机构：

[1] Natl Dong Hwa Univ, Dept Informat Engn, Taoyuan, Taiwan

[2] Chung Shan Inst Sci & Technol, Inst Elect Engn, Tao Yuan, Taiwan

[3] Macronix Inc, Hsinchu, Taiwan

[4] Ming Hsin Inst Technol, Dept Elect Engn, Hsinchu, Taiwan

[5] Chang Gung Univ, Dept Elect Engn, Tao Yuan, Taiwan

[6] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan

[7] Natl Taiwan Univ, Dept Elect Engn, Taipei, Taiwan

[8] AT&T Bell Labs, DSP Res Dept, Murray Hill, NJ 07974 USA

来源：

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 1998年 / 44卷 / 03期

关键词：

D O I：

10.1109/30.713173

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

引用

页码：623 / 629

页数：7

共 6 条

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